Chapter 4.1: Central Processing Unit (CPU) Architecture
9618 AS Computer Science
📚 Learning Objectives
Show understanding of Von Neumann model and stored program concept
Show understanding of purpose and role of registers (general purpose and special purpose)
Show understanding of ALU, Control Unit, System Clock, and IAS
Understand data transfer using address bus, data bus, and control bus
Understand factors contributing to system performance
Understand ports: USB, HDMI, VGA
Describe stages of Fetch-Execute cycle and register transfer notation
Show understanding of interrupts and ISR handling
🌟 Did You Know?
Early computers were fed data while machines were running - it was not possible to store programs or data. John Von Neumann introduced the revolutionary idea of the stored program computer, realizing that data and programs are of the same type and can use the same memory!
1. The Von Neumann Model
John von Neumann was the first person to describe the basic principles of a computer system and its architecture in a publication. The model has the following basic features:
📖 Key Features of Von Neumann Architecture
There is a processor - the Central Processing Unit (CPU)
The processor has direct access to memory
Computer memories can store programs as well as data
The stored program consists of individual instructions
The processor executes instructions sequentially
1.1 The Stored Program Concept
A Stored-Program digital computer keeps its programmed instructions, as well as its data, in read-write, random-access memory (RAM). This was revolutionary because:
Previously, data and programs were stored in separate memories
Von Neumann realized that data and programs are somewhat of the same type
Both can use the same memory
Instructions can be executed in sequential order
💡 Exam Tip
The Von Neumann architecture introduces two key concepts: ADDRESSES (indicate where data is stored) and REGISTERS (needed so data can be manipulated within the computer). Remember: the stored program concept means instructions and data share the same memory!
2. CPU Components
The CPU is the electronic circuit responsible for executing instructions of a computer program. It processes data, performs calculations, and makes decisions.
Carries out operations while a program is being run
A computer can have more than one ALU (fixed-point and floating-point)
Multiplication and division are carried out by sequences of addition, subtraction, and shifting
🌟 ALU and Accumulator
The Accumulator is a temporary register used when carrying out ALU calculations. It receives the results of any calculations that have taken place in the ALU.
2.2 Control Unit (CU)
📖 What is the Control Unit?
Reads an instruction from memory (address stored in PC)
Interprets/decodes the instruction
Generates signals along the control bus to tell components what to do
Ensures synchronization of data flow throughout the computer
Controls operation of CPU, memory, and I/O devices
Coordinates all other parts of the CPU
2.3 System Clock
📝 System Clock Functions
Produces timing signals on the control bus
Ensures vital synchronization takes place
Without the clock, the computer would simply crash
Two types: Internal Clock (controls cycles within processor) and System Clock (controls activities outside processor)
3. Registers
Registers are extremely small, extremely fast memory located in the CPU. They hold small amounts of data needed as part of the fetch-execute cycle. Registers can be General Purpose or Special Purpose.
3.1 General Purpose vs Special Purpose
Type
Description
Example
General Purpose
Can store any data the CPU is currently working on; flexible and can be used for various operations
Accumulator (ACC)
Special Purpose
Has a dedicated role within the operation of the CPU; controls or tracks data
PC, MAR, MDR, CIR, IX, SR
3.2 Special Purpose Registers
📖 Program Counter (PC)
Holds the memory address of the next instruction to be executed
Increments by 1 as the fetch-decode-execute cycle runs
Updated after each instruction is fetched
📖 Memory Address Register (MAR)
Holds the memory address of where data or instructions are to be fetched from or written to
Used to access data and instructions from memory during execution
📖 Memory Data Register (MDR)
Stores the data or instruction which has been fetched from memory
Acts like a buffer between the CPU and memory
Also holds data to be written to memory
📖 Current Instruction Register (CIR)
Stores the instruction the CPU is currently decoding or executing
Instruction is fetched from memory and stored here
3.3 Accumulator (ACC)
📖 Accumulator
Stores the results of any calculations from the ALU
Used as a temporary register for arithmetic and logic operations
Can be a general purpose register
Receives results for use in the next Fetch-Decode-Execute cycle
3.4 Index Register (IX)
📖 Index Register
Also known as base register
Stores a value that can be added to an address
Used for indexed addressing mode
Modifies operand addresses during program execution
3.5 Status Register (SR)
📖 Status Register (Flag Register)
Contains information about the state of the processor
Each bit is known as a flag
Reflects the outcome of CPU operations
Flag
Symbol
When Set ( = 1)
Carry Flag
C
There is a CARRY following an addition operation
Negative Flag
N
Result of calculation yields a NEGATIVE value
Overflow Flag
V
Arithmetic operation results in an OVERFLOW
Zero Flag
Z
Result of arithmetic or logic operation is ZERO
3.6 Immediate Access Store (IAS)
📝 IAS (Primary Memory/RAM)
Another name for primary (RAM) memory
Holds all data and programs that the processor needs to access
CPU takes data from backing store and puts into IAS temporarily
Read/write operations using IAS are considerably faster than backing store
Key data needed by applications is stored temporarily to speed up operations
4. System Buses
Components within the CPU and wider computer system are connected by buses. A bus is a set of parallel wires through which data/signals are transmitted from one component to another.
4.1 Address Bus
📖 Address Bus Characteristics
Carries addresses throughout computer system between CPU and memory
Unidirectional - bits travel in ONE direction only
Prevents addresses being carried back to CPU
Width determines maximum addressable memory locations
Example: A 16-bit address bus can address 216 = 65,536 memory locations. A 32-bit address bus allows 4,294,967,296 memory locations to be simultaneously addressed.
4.2 Data Bus
📖 Data Bus Characteristics
Bidirectional - allows data to be sent in BOTH directions
Carries data from CPU to memory and vice versa
Also connects to and from I/O devices
Data can be an address, instruction, or numerical value
Wider bus = larger word length that can be transported
4.3 Control Bus
📖 Control Bus Characteristics
Bidirectional - carries signals both ways
Carries signals from CU to all other computer components
Usually 8-bits wide since it only carries control signals
Transmits timing signals for synchronization
Indicates whether to initiate a READ or WRITE operation
💡 Exam Tip
Remember: Address Bus = Unidirectional (CPU to memory only), Data Bus = Bidirectional (both directions). Wider buses = better performance because more data can be transferred in a single operation!
5. CPU Performance Factors
CPU performance is affected by several key characteristics. Understanding these factors helps explain why some computers perform better than others.
5.1 Clock Speed
📖 Clock Speed Explained
Controls timing of operations inside the CPU
Constantly switches between 0 and 1 - each switch is a state change
1 cycle per second = 1 Hz
Typical clock speed: 2-4 GHz (billions of cycles per second)
Higher clock speed = more instructions per second
A 3.2 GHz processor can process 3.2 billion processes per second (theoretically)
⚠️ Important
Higher clock speed doesn't always mean better overall performance! Using a clock speed higher than the computer was designed for can lead to unsynchronized operations and the computer may crash.
5.2 Number of Cores
📖 What is a Core?
A core acts like a mini CPU - can fetch, decode, and execute on its own
Each core has its own: CU, ALU, and Registers
Dual-core = 2 cores, Quad-core = 4 cores
More cores = parallel processing, multiple instructions at same time
Dual-core is NOT always twice as fast as single-core. Some time is used for organizing tasks between cores, and not all tasks can be split across cores. Some tasks are sequential and must be done step-by-step.
5.3 Cache Memory
📖 What is Cache Memory?
Part of primary storage - stores frequently used data and instructions
Located closer to CPU than RAM, so faster to access
Uses SRAM (faster) while main memory uses DRAM
When processor reads memory, it checks cache first
More cache = less time waiting for data from RAM
Modern CPUs have cache up to 1-2 MB (or more)
Cache Level
Location
Speed
Size
Level 1 (L1)
Inside each CPU core
Fastest
Smallest
Level 2 (L2)
Inside or near each core
Fast
Medium
Level 3 (L3)
Shared by all cores
Slower than L1/L2
Largest
5.4 Bus Width and Word Length
📖 Bus Width
Number of bits a bus can carry at once
Wider bus = more bits transferred in single operation
32-bit bus transfers 32 bits at a time; 64-bit transfers 64 bits
Wider data bus = faster processing, more efficient memory access
Word length: number of bits CPU can handle simultaneously
Historical Examples:
• 8088 processor: 4.77 MHz, 8-bit word length
• 80486 processor: 50-80 MHz, 32-bit word length
• Pentium 4: 1.5-3.2 GHz, 64-bit word length
6. Computer Ports
Input and output devices are connected to a computer via ports. The interaction of ports with connected devices is controlled by the control unit.
6.1 Universal Serial Bus (USB)
📖 USB Characteristics
Widely used standard for transmitting data between devices
Serial communication method, operates asynchronously
Four-wired shielded cable: 2 for power/earth, 2 for data transmission
Hot-swappable - devices can be connected while computer is running
Automatically detects devices and loads appropriate drivers
USB-C: Latest standard - small size, fast transfer, carries power
Mini/Micro USB: Mobile devices, older smartphones
Advantages of USB
Disadvantages of USB
Devices automatically detected and drivers loaded
Maximum cable length ~5 metres
Connectors fit only one way - prevents incorrect connections
Older versions have limited transmission rates
Industry standard - considerable support available
Old standards may not be supported in future
Multiple data transmission rates supported
Newer standards backward compatible
6.2 High Definition Multimedia Interface (HDMI)
📖 HDMI Characteristics
Digital port that sends both video and audio output
Replaces older VGA analogue systems
Supports high-definition signals up to 10 Gbps
Maximum resolution: 4K (3840 × 2160), Ultra High Speed up to 10K at 120FPS
Uses HDCP (High-bandwidth Digital Content Protection) for security
Remote control signals can pass back along cable
🌟 HDMI Authentication
HDMI uses authentication protocol: devices check for authentication key before sending data. If key is authenticated, "handshaking" occurs and data transmission begins. This helps prevent unauthorized copying of protected content.
6.3 Video Graphics Array (VGA)
📖 VGA Characteristics
Introduced in the 1980s - now considered outdated
Analogue signal - lower image quality over long cables
Maximum resolution: 640 × 480 pixels
Refresh rate: up to 60 Hz, but only 16 colors at that rate
Only transmits video - no audio
Being phased out in favor of HDMI
Feature
HDMI
VGA
Signal Type
Digital
Analogue
Max Resolution
4K/10K
640 × 480
Audio Support
Yes (video + audio)
No (video only)
Security
HDCP protection
None
Cable Length
Good signal over distance
Signal loss over long cables
Status
Current standard
Being phased out
7. Fetch-Execute Cycle
The fetch-execute cycle (also called fetch-decode-execute cycle) is the process that the CPU goes through repeatedly to process instructions.
7.1 The Three Stages
📝 Three Stages of F-E Cycle
Fetch: Retrieve an instruction from memory - supply the address and receive the instruction
Decode: Translate the retrieved instruction into a series of computer commands - interpret the instruction
Execute: Execute the computer commands - carry out the required action
7.2 Detailed Steps
📖 Fetch Stage (Steps 1-4)
Load the address from PC into MAR
Increment the PC by 1
Load the instruction from memory address (in MAR) into MDR
Load the instruction from MDR into CIR
📖 Decode Stage (Step 5)
Decode the instruction in the CIR - CU interprets what to do
📖 Execute Stage (Steps 6-7)
If jump instruction: load address part into PC and reset to step 1
Execute the instruction
Reset and go back to step 1
🌟 Pipelining
Processors use pipelining - a micro-processing technique that handles multiple stages of different computer instructions at once. This allows the processor to begin fetching a second instruction before completing the cycle for another instruction!
7.3 Fetch-Execute Cycle Flowchart
💡 Exam Tip
Remember the order: PC → MAR → MDR → CIR. The PC holds the address, MAR receives it, MDR gets the instruction from that address, and CIR stores the current instruction for decoding. Double brackets [[MAR]] mean "data at the address stored in MAR"!
8. Register Transfer Notation (RTN)
Register Transfer Notation (RTN) is a way of describing how data moves between registers in a CPU during the fetch-execute cycle. It uses symbols to represent registers and arrows to show data transfer.
8.1 Common RTN Symbols
Symbol
Meaning
←
Data is transferred INTO a register
PC
Program Counter
MAR
Memory Address Register
MDR
Memory Data Register
CIR
Current Instruction Register
ACC
Accumulator
RAM[ ]
Memory location at address
[[ ]]
Data at address (double brackets = indirect)
8.2 RTN Examples
📝 Fetch Stage in RTN
MAR ← [PC] : Copy address from PC to MAR
MDR ← RAM[MAR] : Read instruction from memory into MDR
PC ← [PC] + 1 : Increment PC for next instruction
CIR ← [MDR] : Copy instruction from MDR to CIR
📝 Execute Examples in RTN
LDA X (Load value from memory location X into ACC):
MAR ← operand
MDR ← RAM[MAR]
ACC ← [MDR]
STA X (Store ACC value into memory location X):
MAR ← operand
MDR ← [ACC]
RAM[MAR] ← [MDR]
ADD X (Add value from memory location X to ACC):
MAR ← operand
MDR ← RAM[MAR]
ACC ← [ACC] + [MDR]
BRZ X (Branch to X if ACC = 0):
If [ACC] = 0 then PC ← operand
🧠 Memory Trick
The arrow ← always points LEFT to where data is being saved (just like variable assignment in Python!). Double brackets [[ ]] mean "go to address, then get data at that address" - like a treasure map!
9. Interrupts
An interrupt is a signal sent from a device or software to the processor that causes it to temporarily stop what it is doing and service the interrupt.
9.1 Purpose and Role of Interrupts
📖 Why Interrupts are Used
Real-time Event Handling: Hardware errors, signals from I/O devices (e.g., disk failure)
Multitasking: Suspending one application to switch to another
Timer Signals: Time-based events and scheduling
9.2 Types of Interrupts
Type
Definition
Examples
Hardware Interrupts
Generated by external devices
Keyboard input, mouse movements, disk I/O
Software Interrupts
Triggered by software or OS
File requests, division by zero
Trap Interrupts
Intentionally triggered by a program
Debugging, handling unexpected errors
9.3 Interrupt Service Routine (ISR)
📖 What is an ISR?
A special function that handles a particular interrupt type
Each type of interrupt has a corresponding routine
Examples: printer jam routine, disk failure routine, network error routine
ISRs should be concise and efficient to minimize execution time
📝 How Interrupts are Handled
At end of each F-E cycle, processor checks for interrupt(s)
Check if interrupt flag is set in interrupt register
Identify source of interrupt and check priority
If priority is high enough, save register contents to stack (PCB)
Call Interrupt Service Routine (ISR)
Address of ISR loaded into PC
ISR code is executed
When complete, restore registers from stack
Re-enable lower priority interrupts
Continue with next F-E cycle
9.4 Interrupt Priority and Nesting
📖 Priority Handling
Processor can acknowledge and switch to a higher-priority interrupt
Prioritizing is vital because many things can go wrong simultaneously
Lower-priority ISRs may be suspended until higher-priority ISR completes
Nesting: Ability to handle interrupts within interrupts
⚠️ Important
If priority of interrupt is lower than current process, current process continues. Only higher priority interrupts will cause the processor to switch tasks. Proper management of nested interrupts avoids conflicts and ensures system stability.
Example: Keyboard Interrupt Handling
1. Interrupt flag raised in interrupt register
2. System finishes current F-E cycle
3. Check for higher priority interrupt
4. If none, save register contents to stack
5. Execute appropriate ISR
6. Restore registers from stack
7. Return to original process
10. Glossary
📖 Key Terms
ALU (Arithmetic Logic Unit) → Component that performs arithmetic and logic operations
Accumulator (ACC) → Register that stores results of ALU calculations
Address Bus → Unidirectional bus that carries memory addresses
Cache → Fast memory storing frequently used data close to CPU
Clock Speed → Number of cycles per second, measured in Hz
Control Bus → Bidirectional bus carrying control signals
Control Unit (CU) → Component that manages instruction execution and data flow
Core → Mini CPU with own CU, ALU, and registers
CIR (Current Instruction Register) → Stores instruction being decoded/executed
Data Bus → Bidirectional bus that carries data
Fetch-Execute Cycle → Process of fetching, decoding, and executing instructions
HDMI → Digital port for video and audio output
IAS (Immediate Access Store) → Another name for primary/RAM memory
Interrupt → Signal causing processor to stop and handle an event
ISR (Interrupt Service Routine) → Code that handles specific interrupt type
Index Register (IX) → Register used for indexed addressing
MAR (Memory Address Register) → Holds memory address for data access
MDR (Memory Data Register) → Stores data fetched from or to be written to memory
PC (Program Counter) → Holds address of next instruction to execute